Field of the Invention
Embodiments of the present invention relate generally to memory architecture and, more specifically, to power savings via selection of an SRAM power source.
Description of the Related Art
In computer systems, generally, and in graphics processing units (GPUs), in particular, power consumption is a critical parameter. As computing technology migrates to mobile and handheld applications, the benefit of further reduction of power consumption becomes increasingly important. One technique for reducing power consumption is to reduce the overall system voltage. However, many computer systems include SRAM cells, which require some minimum voltage in order to accurately retain the state of stored data. This minimum voltage imposes a lower bound on the system voltage.
This limiting scenario may be overcome by establishing separate power domains for the system voltage and the SRAM circuits. SRAM circuits are then maintained at a higher voltage, and the processors and logic circuitry may operate with a lower voltage. With this approach, the difference between the level of the system voltage domain and that of the SRAM voltage domain must be equalized. Typically, level shifting circuits are utilized to allow the processors and logic to access the SRAM cells across the discontinuous voltage boundary.
One drawback to the above approach is that the level shifting circuits must be powered by the higher SRAM voltage, thus consuming more power than comparable logic domain circuits. The level shifting circuits add significantly to the chip area required due to the large number of interfaces between logic and SRAM. Further, unless the two voltage domains track closely, timing issues arise. If the logic voltage is raised to improve performance and rises above the SRAM voltage, the read noise margin may be reduced, and the SRAM can suffer read disturbances. Conversely, if the logic voltage is lowered below the SRAM voltage to reduce power consumption, timing delays may make writing to the SRAM cell more difficult. As a result, timing issues can limit the maximum level of the logic supply voltage, which limits optimum performance. Further, the minimum voltage that supports SRAM interface and write integrity imposes a lower bound that limits optimum power reduction.
As the foregoing illustrates, what is needed in the art is an effective technique for reducing power usage associated with SRAM cells.